Art-Semi

Load Boards

UltraFlex Load Board

DUT Count : 748FCMSP 8Para
Size : 580 x 404mm
Thickness : 4.8mm+/-0.2mm
Material : FR-4
Option : HPL/0.4P/Back-drill
Net Count : 3013 (including I/O & Power)
Connections : closing to 8000
Layers : 46/56 in total
Component Count : 1850
DUT pitch : 1mm

IntegraFLEX Load Board

Net Count : 1087 (including I/O & Power)
Connections : closing to 4500
Layers : 28 in total
Component Count : 629
DUT pitch : 1mm

ETS364 Load Board

Net Count : 1347 (including I/O & Power)
Connections : closing to 4000
Layers : 44 in total
Component Count : 1683
DUT pitch : 0.4 mm

T2000 Load Board

DUT Count : 100FCFBGA 16Para
Size : 550 x 480mm
Thickness : 4.8mm+/-0.2mm
Material : FR-4
Option : HPL/0.4P/Back-drill
Net Count : 2710 (including I/O & Power)
Connections : closing to 11300
Layers : 30/32 in total
Component Count : 1280
DUT pitch : 1mm

J750 Load Board

Net Count : 1366 (including I/O & Power)
Connections : closing to 3000
Layers : 28 in total
Component Count : 819
DUT pitch : 0.65 mm

T6573 Load Board

Net Count : 712 (including I/O & Power)
Layers : 22 in total
Component Count : 271

112G Advantest 93K Load Board

Net Count : 725 (including I/O & Power)
Layers : 50 in total
Component Count : 1265

RASP Square Load Board

Net Count : 3500 (including I/O & Power)
Layers : 38 in total
Component Count : 1310

NI STS Load Board

Net Count : 700 (including I/O & Power)
Connections : closing to 1400
Layers : 18 in total
Component Count : 400
DUT pitch : 0.35mm

UltraFlex Load Board

Net Count : 3155 (including I/O & Power)
Layers : 40 in total
Component Count : 2355

Probe Cards

UltraFlex Probe Card

Net Count : 1200 (including I/O & Power)
Connections : closing to 2000
Layers : 28 in total
Component Count : 594
DUT pitch : 0.4 mm

J750 Probe Card

Net Count : 1368 (including I/O & Power)
Connections : closing to 3500
Layers : 32 in total
Component Count : 242
DUT pitch : 1.4 mm

T6372 Probe Card

Net Count : 3200 (including I/O & Power)
Connections : closing to 4800
Layers : 44 in total
Component Count : 314
Device pitch / Pin count : 1.5 mm / 3200 pins

T6373 Probe Card

Net Count : 1850 (including I/O & Power)
Connections : closing to 2500
Layers : 46 in total
Component Count : 359
Device pitch : 0.65 mm

Probe Interface Board

UltraFlex PIB

Net Count : 1900 (including I/O & Power)
Layers : 28 in total
Component Count : 73

IntegraFLEX PIB

Net Count : 774 (including I/O & Power)
Connections : closing to 2000
Layers : 24 in total
Component Count : 228

Characterization Boards

PM8667 Char Board

Net Count : 1350 (including I/O & Power)
Connections : closing to 5000
Layers : 24 in total
Component Count : 1950
Device pitch / Pin count : 0.65mm / 1369 pins

PM8667 Char Board

Net Count : 1350 (including I/O & Power)
Connections : closing to 5000
Layers : 24 in total
Component Count : 1950
Device pitch / Pin count : 0.65mm / 1369 pins

Full Turn Key Solution

Post Silicon Engineering

Our process encompasses various stages, each contributing to the successful design and development of integrated circuits (ICs) or chips. Here are the key steps involved in the design process:

Requirement Specification

We begin by thoroughly understanding the customer's requirements and specifications, including the chip's purpose, intended application, performance goals, power constraints, and other design considerations.

Architecture Design

Next, we determine the high-level architecture of the chip, identifying major functional blocks, their interconnections, and the overall system organization. This helps define the chip's functionality and performance capabilities.

Functional Design

Our engineers break down the chip's architecture into smaller functional units, specifying the behavior and functionality of each unit, considering inputs, outputs, and internal operations.

Register Transfer Level (RTL) Design

Our RTL design phase involves representing the chip's functionality using a hardware description language (HDL) like Verilog or VHDL. Our engineers create a detailed description of the chip's behavior at the register transfer level.

Functional Verification

Art-Semi conducts an extensive verification to ensure the chip functions as intended. Techniques such as simulation and formal verification are employed by our teamto test the chip's behavior against specified requirements, identifying and resolving any functional issues or bugs.

Physical Design

We convert logical design into a physical layout that can be manufactured. This involves tasks like floor planning, placement, routing, and consideration of factors like power distribution, signal integrity, and manufacturability.

Design for Manufacturability (DFM)

Our engineers optimize the layout to ensure the design can be fabricated reliably and cost-effectively, employing techniques such as reducing design variations, optimizing lithography masks, and improving yield.

Tapeout

Our team prepares chip design files for manufacturing by generating a set of files called the tapeout, providing the necessary information for the fabrication facility (fab) to manufacture the chip.

Fabrication and Packaging

The tapeout files are sent to the fab, where the chip is manufactured on a silicon wafer using various processes. After fabrication, the wafer is diced into individual chips, which are then packaged to protect them and provide electrical connections for integration into electronic devices.

Testing and Characterization

Fabricated chips undergo extensive testing carried out by Art-Semi’s expert team which includes functional, performance, and reliability testing. Chips are characterized to determine their electrical characteristics such as power consumption, timing, and signal integrity.

Post-Silicon Validation

Further validation and testing is conducted by Art-Semi team after deploying chips in real-world applications, ensuring performance and reliability in target systems and identifying any system-level issues.